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<title>FCHS—Change Sign </title></head>
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<h1>FCHS—Change Sign</h1>
<table>
<tr>
<th>Opcode</th>
<th>Instruction</th>
<th>64-Bit Mode</th>
<th>Compat/Leg Mode</th>
<th>Description</th></tr>
<tr>
<td>D9 E0</td>
<td>FCHS</td>
<td>Valid</td>
<td>Valid</td>
<td>Complements sign of ST(0).</td></tr></table>
<h2>Description</h2>
<p>Complements the sign bit of ST(0). This operation changes a positive value into a negative value of equal magni-tude or vice versa. The following table shows the results obtained when changing the sign of various classes of numbers.</p>
<h3>Table 3-20.  FCHS Results</h3>
<table>
<tr>
<th>ST(0) SRC</th>
<th>ST(0) DEST</th></tr>
<tr>
<td>− ∞</td>
<td>+ ∞</td></tr>
<tr>
<td>− F</td>
<td>+ F</td></tr>
<tr>
<td>− 0</td>
<td>+ 0</td></tr>
<tr>
<td>+ 0</td>
<td>− 0</td></tr>
<tr>
<td>+ F</td>
<td>− F</td></tr>
<tr>
<td>+ ∞</td>
<td>− ∞</td></tr>
<tr>
<td>NaN</td>
<td>NaN</td></tr></table>
<p><strong>NOTES:</strong></p>
<p>*</p>
<p>F means finite floating-point value.</p>
<p>This instruction’s operation is the same in non-64-bit modes and 64-bit mode.</p>
<h2>Operation</h2>
<pre>SignBit(ST(0)) ← NOT (SignBit(ST(0)));</pre>
<h2>FPU Flags Affected</h2>
<table class="exception-table">
<tr>
<td>C1</td>
<td>Set to 0.</td></tr>
<tr>
<td>C0, C2, C3</td>
<td>Undefined.</td></tr></table>
<h2>Floating-Point Exceptions</h2>
<table class="exception-table">
<tr>
<td>#IS</td>
<td>Stack underflow occurred.</td></tr></table>
<h2>Protected Mode Exceptions</h2>
<table class="exception-table">
<tr>
<td>#NM</td>
<td>CR0.EM[bit 2] or CR0.TS[bit 3] = 1.</td></tr>
<tr>
<td>#UD</td>
<td>If the LOCK prefix is used.</td></tr></table>
<h2>Real-Address Mode Exceptions</h2>
<p>Same exceptions as in protected mode.</p>
<h2>Virtual-8086 Mode Exceptions</h2>
<p>Same exceptions as in protected mode.</p>
<h2>Compatibility Mode Exceptions</h2>
<p>Same exceptions as in protected mode.</p>
<h2>64-Bit Mode Exceptions</h2>
<p>Same exceptions as in protected mode.</p></body></html>